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CS501 Assignment no 01 Spring 2012 Solution has been uploaded

Assignment No. 02
Semester: Spring 2013

CS501: Advanced Computer Architecture

 

 

Total Marks: 20

Due Date:  06-05-13

 

Instructions

Please read the following instructions carefully before assignment submission.

 

 

It should be clear that your assignment will not get any credit if:

 

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).

 

 

Objective

The objective of this assignment is:

 

  • To assess your overall understanding of Register Transfer Language and its notations.
  • To assess your overall understanding of binary encoding of Computer Instructions.
  • To assess your overall understanding of how data is being processed in Registers and memory.

 

 

 

Note:

 

  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 6-10. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

 

 

 

 

 

 

 

Assignment

 

 

Question No 1:                                                 Marks 1+1+1+1+1=5

  Q. 1.                        Briefly explain the following Register Transfer Language (RTL) notations:

 

1)    R [1]           ß  R [2] + (-56)

2)   R[5] ←R[0] ©R[6]/R[3]

3)   R [4] ß  R [3] ~ R [1]

4)   IO[R [4]+1]ß  R[7]]

5)   M[R [1] +13]    ß   R [3]

 

 

Question No 2: Fill the given table by specifying binary encoded values against each instruction.                                                               

Marks 15

Instruction Type OP-Code Ra Rb Rc C1 C2 Addressing mode RTL Description Condition PC status
ori r2, r4, 9  III 01011(11) R2 R4 N/A 09  N/A Immediate R[2]←R [4] ~9  N/A N/A
jnz r1, [27]

 

 II  10010 (18)  R1  N/A  N/A  N/A  27  Relative  R[1] not equal to 0

PC ← PC + 27

 If R not equal to 0  PC ←PC + 27
Out  7,R5(30)  II  11001 (25)  R7  R5 N/A  N/A  30  Displacement  IO [R[5]+30←R[27]  N/A  N/A
Load R[6]+99]  III  11101 (29)  R1  R6  N/A  99  N/A  Displacement  R[1]←M[R[6]+99  N/A  N/A
Jmi  R3,[7]  II  100001 (17)  R3  N/A  N/A  N/A  07  Relative  R[1]<0;

PC←PC+7

 If R3 < 0  PC←PC+7

 

Note: You may write N/A in a cell not relevant to any instruction.

 

 

 

GOOD LUCK!

 

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One comment

  1. Please Discuss about the First Question here…………

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