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Solution of Assignment No. 01 |
Total Marks: 20
Due Date: 03/May/2013 |
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Instructions: Please read the following instructions carefully before submitting assignment:
Objectives:
To understand the use of ISR and its services.
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| For any query about the assignment, contact at cs609@vu.edu.pk | ||
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Assignment Questions |
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Question 1: Marks 10
Answer the following questions precisely. Do not include irrelevant data in your answers. Any answer with more than three lines will neglect your marks. (2 marks for each) Q1. Where are the interrupt vectors located in the microprocessors memory? Q2. Which interrupt vectors are reserved by Intel? Q3. Explain the operation of IRET instruction. Q4. List the events that occur when an interrupt becomes active. Q5. Explain the purpose of the trap flag (TF).
Question 2: Marks 10
Write a C program that should write the value of ‘k’ in the keyboard buffer whenever the letter ‘z’ is pressed from keyboard.
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BEST OF LUCK |
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Please post the solution. Thanks.
Q # 1 Solution
(a) interrupt reside in memory and supported by operating system reside in kernal in case of Dos kernal is io.sys.
(b) The first 32 interrupt vector locations are reserved for Intel
(c) In Real Address Mode, iret pops CS, the flags register, and the instruction pointer from the stack and resumes the routine that was interrupted. In Protected Mode, the setting of the nested task flag (NT) determines the action of iret. The IOPL flag register bits are changed when CPL equals 0 and the new flag image is popped from the stack.iret returns from an interrupt procedure without a task switch if NT equals 0. Returned code must be equally or less privileged than the interrupt routine as indicated CS selector RPL bits popped from the stack. If the returned code is less privileged, iret pops SS and the stack pointer from the stack.iret reverses the operation of an INT or CALL that caused the task switch if NT equals 1. The task executing iret is updated and saved in its task segment. The code that follows iret is executed if the task is re-entered.
(e) A trap flag permit operation of a processor in a single step mode. if such a flag is available debugger can use it to step through the execution of a computer program.
(d)
Event that can generate interrupt include a timer overflow or research an assign value, a serial input device has receive a new character, a serial output device is ready to send a new character, an input pin has change state, the system voltage has dropped below a safe level, ADC has finished a new conversion.